Integrated circuits are typically fabricated with multiple levels of patterned metallization electrically separated by interlayer dielectrics that contain vias at selected locations to provide electrical connections between the patterned metallization layers. The patterned metallization layers constitute interconnections between elements of the integrated circuits. As integrated circuits are scaled to smaller dimensions in a continual effort to provide increased performance (e.g. increased device speed and more functions within a given area), the interconnection linewidth becomes even narrower, which renders them more susceptible to deleterious effects such as electromigration and stress migration.
The electromigration refers to mass transport of the materials, which comprise the interconnections in response to electrical current conduction. The stress migration refers to mass transport of the interconnection material in response to mechanical stress gradients present in the interconnections which result from thermal expansion coefficient mismatches and compliance mismatches between the conductive runners and surrounding (e.g. overlying and/or underlying) dielectric materials.
Essential to improving the electromigration, stress migration and other properties of the interconnections, is a method for measuring these effects. The typical interconnection test structure is one test line with, for example, 30 samples. Then each sample represents 3.3% cumulative failure rate. However, the quality, such as lifetime, of the interconnections may be predicted based on 0.1% failure rate, and therefore the prediction is performed by extrapolation. However, it has been found not accurate enough as compared to the real situation.
Besides, as the interconnection linewidth shrinks, the width difference between the interconnection test pattern and the line connecting it to the pad for applying a current, a voltage and/or a mechanical stress would be even more distinct. Consequently, a current induced by the electrostatic discharge (ESD) may lead to the burn out of the interconnection test pattern.
Therefore, a more accurate method for measuring a property of interconnections and a structure for the same with the electrostatic discharge (ESD) protection are needed.